Openings

The ESD Research Group at CS Department of University of Verona (Italy) invites applications for:

  • Research Assistant (junior researcher with MSc or equival).
  • Post-Doctoral positions in the area of embedded system design / wireless sensor networks (WSN).

 

Current research projects cover the following topics:

  • Energy management for wireless sensor networks: the candidate is expected to pursue research on energy management strategies to maximixe node lifetime, while ensuring a predefined performance level. In such a context, control policies at the node level must be integrated in a network-wide energy control strategy, that jointly optimize network topology, routing algorithm and transmission protocols.
  • Process control with wireless tags: the candidate is expected to pursue research on the use of a networked embedded architecture to control the fermentative processes for starter cultures used for wine production. In particular, it is necessary to design an open-platform solution in order to apply the architecture to any hardware/software configuration (e.g., PC, Tabled-PC, Palm, touch-screen, mobile terminal, etc.).
  • Development tools for wireless sensor networks: the candidate is expected to pursue research on tools for development, simulation, debugging, and management of applications based on wireless sensor networks. The resulting tools aim at supporting the life cycle of applications based on wireless sensor networks.
  • Development of tool for synthesis and verification of discrete systems: the candidate is expected to pursue research on tools for synthesis and verification of discrete systems. The focus of the activity related to synthesis requires working on a tool for the automatic synthesis of a discrete system (say, a controller) that meets a specification when composed with a context (say a closed-loop composition with a given plant). Applications are controller synthesis, micro-architectural exploration, sequential synthesis. The focus of the activity related to verification will be implementing an automatic tool for mutation analysis of FSM models representing TLM/RTL descriptions, aiming at verifying the correctness of the implementation via simulation.
  • Development of methodologies for TLM to RTL automatic refinement: the candidate is expected to pursue research on automatic synthesis of TLM designs. In particular, the focus of the activity will be in defining a refinement methodology aiming at synthesizing TLM communication modules into RTL models of standard protocols and TLM functionality into RTL models of the same functionality.

Requirements. The candidate:

  • Must have an MSc or Ph.D. degree in Computer Engineering, Computer Science, Electrical Engineering or related discipline by the time of the appointment.
  • Should have research experience demonstrated through publications in international conferences and journals.
  • Should have good skills in programming (C/C++), and verbal and written English.

The position is available immediately for 12 months and extensible based on the performance of the candidate. Interested applicants should send their Curriculum Vitae and a Motivation Letter, both in PDF format, to franco.fummi@univr.it, puting in the subject "ESD openings".